The present invention generally relates to a circuit for adjusting voltage level of data output in a semiconductor memory device and, in particular, to a circuit for adjusting the voltage level of a data output terminal formed in a semiconductor memory device which produces the data in series, thereby having a high speed access time.
Generally, a dynamic random access memory (DRAM) includes a data output buffer at its data output terminal, for buffering the output signals of a sense amplifier and provides the buffered output signal to an output pad or to an output pin. In the data output buffer, differential amplifier output terminals SAS, SAS of the sense amplifier are initially set to a logic "high" and logic "low" levels, or in the alternative they are set to an intermediate level (i.e., a high impedance). In the meanwhile, if the output terminals SAS, SAS change their logic states to logic "low" or "high" because of data sensed (read) from a memory cell, then the data is buffered and coupled to the output terminals in response to a data-output-enable clock.
FIG. 1 shows a known data output buffer. As shown in the drawing, the prior data output buffer includes two NMOS transistors M1, M2 which are coupled in series between a power supply terminal (Vcc PIN) 14 and a ground refererce terminal (Vss PIN) 16. A connection node 20 formed between the serial-connected NMOS transistors is connected to an output terminal (D.sub.OUT PIN) 18 by way of an inductor L2. Therefore, the data output buffer outputs data to the node 20 according to the logic data which is inputted to each gate of the transistors M1, M2. Further, there is provided a data output driving controller 12 for receiving the output data SAS, SAS of a differential sense amplifier (not shown) and for also receiving a data-output-enable clock .phi.OE. These signals are applied to a data buffer in the data output driving controller 12. Then, the data output driving controller 12 applies the output data SAS, SAS of the differential amplifier to each gate of the NMOS transistors M1, M2, when enabled by the data-output-enable clock .phi.OE.
In FIG. 1, inductors L1, L2, L3 are the inductance components formed by wire-bonding the chip substrate with each chip terminal. The inductors L1, L2, L3 are connected between the respective pin and the NMOS transistors M1, M2, in a well-known manner. The current I1 will the conducted when the NMOS transistor M1 is turned on and, at the same time, the NMOS transistor M2 is turned off. Therefore the data output terminal 18 will be at a logic "high". On the contrary, the current I2 will be conducted when the NMOS transistors M1, M2 are respectively turned off and turned on, changing the output logic state of the data output terminal 18 to a logic "low".
Referring now to FIG. 2 which is a timing chart for showing the operation of the data output buffer of FIG. 1, this illustrates a general example of fast page mode of operation in a DRAM. That is, RAS represents a row address strobe; CAS represents a column address strobe; .phi.OE represents a data-output-enable clock; CA represents a column address; A and B represent the data output at the output terminals A', B' of the data output driving controller 12; I1 and I2 represent the current flowing through the NMOS transistors M1 and M2, respectively; and D.sub.OUT represents the output data of the data output terminal 18.
Referring now to FIG. 3 which is another timing chart for showing the operation of the data output buffer circuit of FIG. 1, this illustrates a static column operating mode in a DRAM. The like notations in this drawing represent waveforms of the like data shown in FIG. 2.
First, the exemplary operation of the fast page mode in a DRAM having the known data output buffer of FIG. 1 will be explained hereinbelow, with reference to the waveforms of FIG. 2.
In the conventional DRAM, if the row address strobe RAS and column address strobe CAS are at the logic "low" state concurrently, row address and column address signals are sequentially sent to an addressed memory cell so as to read out the data stored therein. The data read out from the addressed memory cell is then amplified by means of the sense amplifier (not shown) and applied as the data signals SAS, SAS to the data output driving controller 12 of FIG. 1.
At about this moment, the data output enable clock .phi.OE is inputted to the data output driving controller 12 with a given delay, according to the change of column address strobe CAS which now changes from a non-active "low" state to an active "high" state.
The data output driving controller 12 receives the enable clock .phi.OE and provides at its output terminals A', B' with the data SAS, SAS signals generated by the sense amplifier.
Assuming that the output data SAS, SAS of the sense amplifier correspond to a logic "1" which is read out of an addressed memory cell according to a first column address COL1, the data output driving controller 12 provides a logic "high" (30)M1 to the gate of the NMOS transistor Ml and a logic "low" to the gate of the NMOS transistor M2. Accordingly, the transistor Ml is turned on and the transistor M2 is turned off. So, the drain voltage of the transistor M1 will be applied to the node 20. The current I1 is conducted from the power supply terminal 14 through the inductor L1 and the NMOS transistor M1 to the output terminal 18 through the node 20.
Since the current I1 at the node 20 is conducted to the output terminal 18 through the inductor L2 which is wire-bonded between the node 20 and the output terminal 18, as shown in the drawing, the voltage at the output terminal 18 changes from the high-impedance voltage 2e as shown in FIG. 2 to the logic "high" voltage 2a. In this case, output noises are generated because of the inductor L1 of the power supply terminal 14 and the inductor L2 of the output terminal 18. Thus, for example, the initial portion of the output data having a logic "high" state will have a noise width according to the following equation (1). ##EQU1##
After the logic data "1" has been read out of the memory cell designated by the first column address COL1 as mentioned above, the column address strobe CAS holds the logic "high" state for a given period of time and then returns to the logic "low" state after receiving the second column address COL2, as shown in FIG. 2.
Therefore, from the not illustrated memory cell corresponding to the second column address COL2 is read out the data stored thereinto and is applied as the data SAS, SAS to the data output driving controller 12 of FIG. 1, after amplified by means of the sense amplifier in the same manner as described before. At the same time, to the data output driving controller 12 is applied the enable clock .phi.OE which changes to logic "low" according to the column address strobe CAS, as shown in FIG. 2. Further, if the logic state of the data outputted from the memory cell is logic "0", the data outputted from the data output driving controller 12 is the data A, B in FIG. 2. Thus, the NMOS transistor M1 is turned off while the NMOS transistor M2 is turned on. Accordingly, the current I2 as shown in FIG. 2 will flow from the output terminal 18 to the ground reference terminal 16 through the node 20. Since the current I2 flows by way of the inductor L3 coupled to the ground reference terminal 16 and the inductor L2 coupled to the output terminal 18, the data output at the output terminal 18 goes to the logic "low" state as shown in 2b of FIG. 2. In this case,.the noise width of output data produced at the output terminal 18 will be determined by the inductors L2, L3 and is given in form of the following equation (2). ##EQU2##
However, when a semiconductor memory device having the data output buffer as in FIG. 1 is operated in the fast page mode with an extremely short period, the following problems will arise.
Namely, in case the data of the preceding cycle had an extremely short precharging time, the voltage of the data output terminal 18 may not return to the high-impedance voltage level (2e of FIG. 2) for a sufficient length of time before the data of the current cycle is provided at the output. Therefore, if the data output of the preceding cycle and the data output of the current cycle are opposite in their phase or voltage level, the data output speed will be relatively lowered because of the wide swing in voltage at the data output terminal 18. In addition, the noise width of the data output from the output terminal 18 will become wider because of the inductors L1, L2, and L3 (See 2d of FIG. 2).
Next, an exemplary operation of the static column mode in a semiconductor memory device having the data output buffer as shown in FIG. 1 will be described hereinbelow, with reference to FIG. 3.
As shown in FIG. 3, when the row address strobe RAS goes to the active "low" state, a semiconductor memory device operating in the static column mode is addressed by the row address ROW as in usual operation. With the sequential receiving of the first and second column address signals COL1 COL2 as illustrated in FIG. 3 and, at the same time, the transition of the column address strobe CAS to the active "low" state, the data stored in a memory cell (not shown) which is addressed by the row address and column address signals caused by the row address strobe RAS will be accessed (read out).
Thereafter, the data read out from the memory cell by the above address designation is amplified by means of the sense amplifier in such a manner as described above. The output data SAS, SAS are applied to the data output driving controller 12 in FIG. 1. At about the same time, the enable clock .phi.OE generated from the column address strobe CAS is applied to the data output driving controller 12 after delaying a given period of time. The data output driving controller 12 receives the enable clock .phi.OE and provides at its output terminals A', B' the data SAS, SAS.
If the data accessed (read out) from a memory, cell by the first column address COLl of FIG. 1 is a logic "1" and the data accessed by the second column address COL2 is logic "0" which is opposite to the preceding logic state, then the data output driving controller 12 outputs the data A, B of FIG. 3 to the output terminals A', B' thereof. Therefore, the output data of the output terminal 18 is initially set to the high-impedance voltage as illustrated at 3c of FIG. 3. The logic "1" illustrated at 3a or logic "0" illustrated at 3b of FIG. 3 is buffered to the output terminal 18.
However, when a semiconductor memory device having the data output buffer of FIG. 1 is operated in the static column mode, the following problems will arise.
When the phase of the preceding data output is opposite that of the current data output, the precharging time required for the data output to return to the voltage level of the high-impedance state is usually not assigned. Therefore, the voltage level of the data output terminal 18 will swing more widely. As a result, the data access speed (output speed) is reduced, compared with the case when the data is generated under the condition that the output terminal 18 is always at the high-impedance voltage (3c of FIG. 3).
Further, both the current I1 flowing from the power supply terminal 14 to the output terminal 18 and the current I2 flowing from the output terminal 18 to the ground reference terminal 16 will be substantially increased, causing the noise width to increase.